AsmJit
Low-Latency Machine Code Generation
AArch64 Backend [¶]
AArch64 backend.
Emitters
- a64::Assembler - AArch64 assembler (must read, provides examples).
- a64::Builder - AArch64 builder.
- a64::Compiler - AArch64 compiler.
- a64::Emitter - AArch64 emitter (abstract).
Supported Instructions
- Emitters:
- a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch64 emitters.
- Instruction representation:
- a64::Inst::Id - instruction identifiers.
Register Operands
- a64::Gp - General purpose register (abstracts 32-bit and 64-bit general purpose registers).
- a64::Vec - Vector register (abstracts B, H, S, D, and Q NEON register with possible element type and index).
Memory Operands
- a64::Mem - AArch64 memory operand that provides support for all ARM addressing features including base, index, pre/post increment, and ARM-specific shift addressing + index extending.
Other
- arm::Shift - Shift operation and value.
- arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.
Namespaces
namespace a64
namespace a64::Inst
namespace a64::Predicate::AT
namespace a64::Predicate::BTI
namespace a64::Predicate::DB
namespace a64::Predicate::DC
namespace a64::Predicate::IC
namespace a64::Predicate::ISB
namespace a64::Predicate::PRFOp
namespace a64::Predicate::PSB
namespace a64::Predicate::TSB
namespace a64::Predicate::PState
namespace a64::Predicate::SysReg
namespace a64::InstDB
Classes
class a64::Assembler
class a64::Builder
class a64::Compiler
struct a64::EmitterExplicitT<This>
class a64::Emitter
struct a64::InstDB::InstInfo
class a64::Gp
class a64::Vec
class a64::Mem
Enumerations
enum class a64::VecElementType : uint32_t
Shift Operation Construction
Memory Operand Construction
class a64::VecElementType : uint32_tenumstrong[¶]
Vector element type (AArch64).
| Constant | Description |
|---|---|
| kNone | No element type specified. |
| kB | Byte elements (B8 or B16). |
| kH | Halfword elements (H4 or H8). |
| kS | Singleword elements (S2 or S4). |
| kD | Doubleword elements (D2). |
| kB4 | Byte elements grouped by 4 bytes (B4).
|
| kH2 | Halfword elements grouped by 2 halfwords (H2).
|
| kMaxValue | Maximum value of VecElementType. |
Shift a64::lsl(uint32_t value)constexprstaticnoexcept[¶]
Constructs a LSL #value shift (logical shift left).
Shift a64::lsr(uint32_t value)constexprstaticnoexcept[¶]
Constructs a LSR #value shift (logical shift right).
Shift a64::asr(uint32_t value)constexprstaticnoexcept[¶]
Constructs a ASR #value shift (arithmetic shift right).
Shift a64::ror(uint32_t value)constexprstaticnoexcept[¶]
Constructs a ROR #value shift (rotate right).
Shift a64::msl(uint32_t value)constexprstaticnoexcept[¶]
Constructs a MSL #value shift (logical shift left filling ones).
Shift a64::uxtb(uint32_t value)constexprstaticnoexcept[¶]
Constructs a UXTB #value extend and shift (unsigned byte extend) (AArch64).
Shift a64::uxth(uint32_t value)constexprstaticnoexcept[¶]
Constructs a UXTH #value extend and shift (unsigned hword extend) (AArch64).
Shift a64::uxtw(uint32_t value)constexprstaticnoexcept[¶]
Constructs a UXTW #value extend and shift (unsigned word extend) (AArch64).
Shift a64::uxtx(uint32_t value)constexprstaticnoexcept[¶]
Constructs a UXTX #value extend and shift (unsigned dword extend) (AArch64).
Shift a64::sxtb(uint32_t value)constexprstaticnoexcept[¶]
Constructs a SXTB #value extend and shift (signed byte extend) (AArch64).
Shift a64::sxth(uint32_t value)constexprstaticnoexcept[¶]
Constructs a SXTH #value extend and shift (signed hword extend) (AArch64).
Shift a64::sxtw(uint32_t value)constexprstaticnoexcept[¶]
Constructs a SXTW #value extend and shift (signed word extend) (AArch64).
Shift a64::sxtx(uint32_t value)constexprstaticnoexcept[¶]
Constructs a SXTX #value extend and shift (signed dword extend) (AArch64).
Mem a64::ptr(const Gp& base, int32_t offset = 0)constexprstaticnoexcept[1/5][¶]
Creates [base, offset] memory operand (offset mode) (AArch64).
Mem a64::ptr_pre(const Gp& base, int32_t offset = 0)constexprstaticnoexcept[1/2][¶]
Creates [base, offset]! memory operand (pre-index mode) (AArch64).
Mem a64::ptr_post(const Gp& base, int32_t offset = 0)constexprstaticnoexcept[1/2][¶]
Creates [base], offset memory operand (post-index mode) (AArch64).
Mem a64::ptr(const Gp& base, const Gp& index)constexprstaticnoexcept[2/5][¶]
Creates [base, index] memory operand (AArch64).
Mem a64::ptr_pre(const Gp& base, const Gp& index)constexprstaticnoexcept[2/2][¶]
Creates [base, index]! memory operand (pre-index mode) (AArch64).
Mem a64::ptr_post(const Gp& base, const Gp& index)constexprstaticnoexcept[2/2][¶]
Creates [base], index memory operand (post-index mode) (AArch64).
Mem a64::ptr(const Gp& base, const Gp& index, const Shift& shift)constexprstaticnoexcept[3/5][¶]
Creates [base, index, SHIFT_OP #shift] memory operand (AArch64).
Mem a64::ptr(const Label& base, int32_t offset = 0)constexprstaticnoexcept[4/5][¶]
Creates [base, offset] memory operand (AArch64).
Mem a64::ptr(uint64_t base)constexprstaticnoexcept[5/5][¶]
Creates [base] absolute memory operand (AArch32 or AArch64).
- Note
- The concept of absolute memory operands doesn't exist on ARM, the ISA only provides PC relative addressing. Absolute memory operands can only be used if it's known that the PC relative offset is encodable and that it would be within the limits. Absolute address is also often output from disassemblers, so AsmJit supports it to make it possible to assemble such output back.