ARM commons shared between AArch32 and AArch64.
Namespaces
- arm - arm namespace provides common functionality for both AArch32 and AArch64 backends.
- a32 - a32 namespace provides support for AArch32 architecture. In addition it includes arm namespace, so you can only use a single namespace when targeting AArch32 architecture.
- a64 - a64 namespace provides support for AArch64 architecture. In addition it includes arm namespace, so you can only use a single namespace when targeting AArch64 architecture.
Emitters
- AArch64
- a32::Assembler - AArch32 assembler (must read, provides examples).
- a64::Assembler - AArch64 assembler (must read, provides examples).
- a32::Builder - AArch32 builder.
- a64::Builder - AArch64 builder.
- a32::Compiler - AArch32 compiler.
- a64::Compiler - AArch64 compiler.
- a32::Emitter - AArch32 emitter (abstract).
- a64::Emitter - AArch64 emitter (abstract).
Supported Instructions
- AArch32:
- Emitters:
- a32::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch32 emitters.
- Instruction representation:
- a32::Inst::Id - instruction identifiers.
- AArch64:
- Emitters:
- a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch64 emitters.
- Instruction representation:
Register Operands
- arm::Reg - Base class for any AArch32/AArch64 register.
Memory Operands
- arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features including base, index, pre/post increment, and ARM-specific shift addressing and index extending.
Other
- arm::Shift - Shift operation and value (both AArch32 and AArch64).
- arm::DataType - Data type that is part of an instruction in AArch32 mode.
- arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.
static
constexpr GpW arm::w(
uint32_t id)
noexceptstatic
constexpr GpX arm::x(
uint32_t id)
noexceptstatic
constexpr VecS arm::s(
uint32_t id)
noexceptstatic
constexpr VecD arm::d(
uint32_t id)
noexceptstatic
constexpr VecV arm::v(
uint32_t id)
noexceptstatic
constexpr Mem arm::ptr(
const Gp& base,
int32_t offset = 0)
noexcept
Condition code (both AArch32 & AArch64).
- Note
- This enumeration doesn't match condition code that is used in AArch32/AArch64 opcodes. In general this condition code is encoded as
(cc - 2) & 0xF
so that kAL
condition code is zero and encoded as 0xE in opcode. This makes it easier to use a condition code as an instruction modifier that defaults to 'al'.
Constant | Description |
---|
kAL | (no condition code) (always)
|
kNA | (not available) (special)
|
kEQ | Z==1 (any_sign ==)
|
kNE | Z==0 (any_sign !=)
|
kCS | C==1 (unsigned >=)
|
kHS | C==1 (unsigned >=)
|
kCC | C==0 (unsigned < )
|
kLO | C==0 (unsigned < )
|
kMI | N==1 (is negative)
|
kPL | N==0 (is positive or zero)
|
kVS | V==1 (is overflow)
|
kVC | V==0 (no overflow)
|
kHI | C==1 & Z==0 (unsigned > )
|
kLS | C==0 | Z==1 (unsigned <=)
|
kGE | N==V (signed >=)
|
kLT | N!=V (signed < )
|
kGT | Z==0 & N==V (signed > )
|
kLE | Z==1 | N!=V (signed <=)
|
kSign | Sign.
|
kNotSign | Not sign.
|
kOverflow | Signed overflow.
|
kNotOverflow | Not signed overflow.
|
kEqual | Equal a == b .
|
kNotEqual | Not Equal a != b .
|
kZero | Zero (alias to equal).
|
kNotZero | Not Zero (alias to Not Equal).
|
kNegative | Negative.
|
kPositive | Positive or zero.
|
kSignedLT | Signed a < b .
|
kSignedLE | Signed a <= b .
|
kSignedGT | Signed a > b .
|
kSignedGE | Signed a >= b .
|
kUnsignedLT | Unsigned a < b .
|
kUnsignedLE | Unsigned a <= b .
|
kUnsignedGT | Unsigned a > b .
|
kUnsignedGE | Unsigned a >= b .
|
kAlways | No condition code (always).
|
kMaxValue | Maximum value of CondCode .
|
Data type that can be encoded with the instruction (AArch32 only).
Constant | Description |
---|
kNone | No data type specified (default for all general purpose instructions).
|
kS8 | 8-bit signed integer, specified as .s8 in assembly.
|
kS16 | 16-bit signed integer, specified as .s16 in assembly.
|
kS32 | 32-bit signed integer, specified as .s32 in assembly.
|
kS64 | 64-bit signed integer, specified as .s64 in assembly.
|
kU8 | 8-bit unsigned integer, specified as .u8 in assembly.
|
kU16 | 16-bit unsigned integer, specified as .u16 in assembly.
|
kU32 | 32-bit unsigned integer, specified as .u32 in assembly.
|
kU64 | 64-bit unsigned integer, specified as .u64 in assembly.
|
kF16 | 16-bit floating point (half precision), specified as .f16 in assembly.
|
kF32 | 32-bit floating point (single precision), specified as .f32 in assembly.
|
kF64 | 64-bit floating point (double precision), specified as .f64 in assembly.
|
kP8 | 8-bit polynomial.
|
kBF16 | 16-bit BF16 floating point.
|
kP64 | 64-bit polynomial.
|
kMaxValue | Maximum value of DataType .
|
class arm::ShiftOp : uint32_tenumstrong◆
Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.
- Note
- The constants are AsmJit specific. The first 5 values describe real constants on ARM32 and AArch64 hardware, however, the addition constants that describe extend modes are specific to AsmJit and would be translated to the AArch64 specific constants by the assembler.
Constant | Description |
---|
kLSL | Shift left logical operation (default).
Available to all ARM architectures.
|
kLSR | Shift right logical operation.
Available to all ARM architectures.
|
kASR | Shift right arithmetic operation.
Available to all ARM architectures.
|
kROR | Rotate right operation (AArch32 only).
|
kRRX | Rotate right with carry operation (encoded as ShiftOp::kROR with zero) (AArch32 only).
|
kMSL | Shift left by filling low order bits with ones.
|
kUXTB | UXTN extend register operation (AArch64 only).
|
kUXTH | UXTH extend register operation (AArch64 only).
|
kUXTW | UXTW extend register operation (AArch64 only).
|
kUXTX | UXTX extend register operation (AArch64 only).
|
kSXTB | SXTB extend register operation (AArch64 only).
|
kSXTH | SXTH extend register operation (AArch64 only).
|
kSXTW | SXTW extend register operation (AArch64 only).
|
kSXTX | SXTX extend register operation (AArch64 only).
|
GpW arm::w(uint32_t id)constexprstaticconstexprnoexcept[1/2]◆
Creates a 32-bit W register operand (ARM/AArch64).
GpX arm::x(uint32_t id)constexprstaticconstexprnoexcept[1/2]◆
Creates a 64-bit X register operand (AArch64).
VecS arm::s(uint32_t id)constexprstaticconstexprnoexcept[1/3]◆
Creates a 32-bit S register operand (ARM/AArch64).
VecD arm::d(uint32_t id)constexprstaticconstexprnoexcept[1/3]◆
Creates a 64-bit D register operand (ARM/AArch64).
VecV arm::v(uint32_t id)constexprstaticconstexprnoexcept[1/2]◆
Creates a 1282-bit V register operand (ARM/AArch64).
Mem arm::ptr(const Gp& base, int32_t offset = 0
)constexprstaticconstexprnoexcept[1/5]◆
Creates [base, offset]
memory operand (offset mode).
Mem arm::ptr_pre(const Gp& base, int32_t offset = 0
)constexprstaticconstexprnoexcept[1/2]◆
Creates [base, offset]!
memory operand (pre-index mode).
Mem arm::ptr_post(const Gp& base, int32_t offset = 0
)constexprstaticconstexprnoexcept[1/2]◆
Creates [base], offset
memory operand (post-index mode).
Mem arm::ptr(const Gp& base, const Gp& index)constexprstaticconstexprnoexcept[2/5]◆
Creates [base, index]
memory operand.
Mem arm::ptr_pre(const Gp& base, const Gp& index)constexprstaticconstexprnoexcept[2/2]◆
Creates [base, index]!
memory operand (pre-index mode).
Mem arm::ptr_post(const Gp& base, const Gp& index)constexprstaticconstexprnoexcept[2/2]◆
Creates [base], index
memory operand (post-index mode).
Mem arm::ptr(const Gp& base, const Gp& index, const Shift& shift)constexprstaticconstexprnoexcept[3/5]◆
Creates [base, index, SHIFT_OP #shift]
memory operand.
Mem arm::ptr(const Label& base, int32_t offset = 0
)constexprstaticconstexprnoexcept[4/5]◆
Creates [base, offset]
memory operand.
Mem arm::ptr(uint64_t base)constexprstaticconstexprnoexcept[5/5]◆
Creates [base]
absolute memory operand.
- Note
- The concept of absolute memory operands doesn't exist on ARM, the ISA only provides PC relative addressing. Absolute memory operands can only be used if it's known that the PC relative offset is encodable and that it would be within the limits. Absolute address is also often output from disassemblers, so AsmJit supports it to make it possible to assemble such output back.
CondCode arm::negateCond(CondCode cond)constexprstaticconstexprnoexcept◆
Negates a condition code.
Shift arm::lsl(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a LSL #value
shift (logical shift left).
Shift arm::lsr(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a LSR #value
shift (logical shift right).
Shift arm::asr(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a ASR #value
shift (arithmetic shift right).
Shift arm::ror(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a ROR #value
shift (rotate right).
Shift arm::rrx()constexprstaticconstexprnoexcept◆
Constructs a RRX
shift (rotate with carry by 1).
Shift arm::msl(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a MSL #value
shift (logical shift left filling ones).
Shift arm::uxtb(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a UXTB #value
extend and shift (unsigned byte extend).
Shift arm::uxth(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a UXTH #value
extend and shift (unsigned hword extend).
Shift arm::uxtw(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a UXTW #value
extend and shift (unsigned word extend).
Shift arm::uxtx(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a UXTX #value
extend and shift (unsigned dword extend).
Shift arm::sxtb(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a SXTB #value
extend and shift (signed byte extend).
Shift arm::sxth(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a SXTH #value
extend and shift (signed hword extend).
Shift arm::sxtw(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a SXTW #value
extend and shift (signed word extend).
Shift arm::sxtx(uint32_t value)constexprstaticconstexprnoexcept◆
Constructs a SXTX #value
extend and shift (signed dword extend).
GpW arm::Gp::w() constnoexcept[2/2]◆
Cast this register to a 32-bit R|W.
GpX arm::Gp::x() constnoexcept[2/2]◆
Cast this register to a 64-bit X.
VecB arm::Vec::b() constnoexcept[1/2]◆
Cast this register to an 8-bit B register (AArch64 only).
VecH arm::Vec::h() constnoexcept[1/2]◆
Cast this register to a 16-bit H register (AArch64 only).
VecS arm::Vec::s() constnoexcept[2/3]◆
Cast this register to a 32-bit S register.
VecD arm::Vec::d() constnoexcept[2/3]◆
Cast this register to a 64-bit D register.
VecV arm::Vec::q() constnoexcept◆
Cast this register to a 128-bit Q register.
VecV arm::Vec::v() constnoexcept[2/2]◆
Cast this register to a 128-bit V register.
VecV arm::Vec::b(uint32_t elementIndex) constnoexcept[2/2]◆
Cast this register to a 128-bit V.B[elementIndex] register.
VecV arm::Vec::h(uint32_t elementIndex) constnoexcept[2/2]◆
Cast this register to a 128-bit V.H[elementIndex] register.
VecV arm::Vec::s(uint32_t elementIndex) constnoexcept[3/3]◆
Cast this register to a 128-bit V.S[elementIndex] register.
VecV arm::Vec::d(uint32_t elementIndex) constnoexcept[3/3]◆
Cast this register to a 128-bit V.D[elementIndex] register.
VecV arm::Vec::h2(uint32_t elementIndex) constnoexcept[1/2]◆
Cast this register to a 128-bit V.H2[elementIndex] register.
VecV arm::Vec::b4(uint32_t elementIndex) constnoexcept◆
Cast this register to a 128-bit V.B4[elementIndex] register.
VecD arm::Vec::b8() constnoexcept◆
Cast this register to V.8B.
VecS arm::Vec::h2() constnoexcept[2/2]◆
Cast this register to V.2H.
VecD arm::Vec::h4() constnoexcept◆
Cast this register to V.4H.
VecD arm::Vec::s2() constnoexcept◆
Cast this register to V.2S.
VecV arm::Vec::b16() constnoexcept◆
Cast this register to V.16B.
VecV arm::Vec::h8() constnoexcept◆
Cast this register to V.8H.
VecV arm::Vec::s4() constnoexcept◆
Cast this register to V.4S.
VecV arm::Vec::d2() constnoexcept◆
Cast this register to V.2D.