Index ⭢ ARM Commons

ARM Commons [¶]

ARM commons shared between AArch32 and AArch64.

Namespaces

arm - arm namespace provides common functionality for both AArch32 and AArch64 backends. arm namespace, so you can only use a single namespace when targeting AArch32 architecture.
a64 - a64 namespace provides support for AArch64 architecture. In addition it includes arm namespace, so you can only use a single namespace when targeting AArch64 architecture.

Emitters

AArch64:
- a64::Assembler - AArch64 assembler (must read, provides examples).
- a64::Builder - AArch64 builder.
- a64::Compiler - AArch64 compiler.
- a64::Emitter - AArch64 emitter (abstract).

Supported Instructions

AArch64:
- Emitters:
  - a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch64 emitters.
- Instruction representation:
  - a64::Inst::Id - instruction identifiers.

ARM Operands

AArch64:
- a64::Gp - 32-bit or 64-bit general purpose register used by AArch64:
- a64::Vec - Vector (SIMD) register.
- a64::Mem - AArch64 memory operand that provides support for all AArch64 addressing features including base, index, pre/post increment, and AArch64 specific shift/extend of memory index.

Memory Operands

Other

arm::Shift - Shift operation and value (both AArch32 and AArch64).
arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.

Namespaces

namespace arm

namespace arm::Utils

Classes

struct arm::Utils::LogicalImm

class arm::Shift

Enumerations

enum class arm::CondCode : uint8_t

enum class arm::OffsetMode : uint32_t

enum class arm::ShiftOp : uint32_t

Functions

static constexpr CondCode arm::reverse_cond(CondCode cond) noexcept

static constexpr CondCode arm::negate_cond(CondCode cond) noexcept

arm::CondCode : uint8_tenum class[¶]

Condition code (both AArch32 & AArch64).

Note

This enumeration doesn't match condition code that is used in AArch32/AArch64 opcodes. In general this condition code is encoded as (cc - 2) & 0xF so that kAL condition code is zero and encoded as 0xE in opcode. This makes it easier to use a condition code as an instruction modifier that defaults to 'al'.

Constant	Description
kAL	(no condition code) (always)
kNA	(not available) (special)
kEQ	Z==1 (any_sign ==)
kNE	Z==0 (any_sign !=)
kCS	C==1 (unsigned >=)
kHS	C==1 (unsigned >=)
kLO	C==0 (unsigned < )
kCC	C==0 (unsigned < )
kMI	N==1 (is negative)
kPL	N==0 (is positive or zero)
kVS	V==1 (is overflow)
kVC	V==0 (no overflow)
kHI	C==1 & Z==0 (unsigned > )
kLS	C==0 \| Z==1 (unsigned <=)
kGE	N==V (signed >=)
kLT	N!=V (signed < )
kGT	Z==0 & N==V (signed > )
kLE	Z==1 \| N!=V (signed <=)
kZero	Zero flag (alias to equal).
kNotZero	Not zero (alias to Not Equal).
kEqual	Equal `a == b`.
kNotEqual	Not Equal `a != b`.
kCarry	Carry flag.
kNotCarry	Not carry.
kSign	Sign flag.
kNotSign	Not sign.
kNegative	Negative.
kPositive	Positive or zero.
kOverflow	Signed overflow.
kNotOverflow	Not signed overflow.
kSignedLT	Signed `a < b`.
kSignedLE	Signed `a <= b`.
kSignedGT	Signed `a > b`.
kSignedGE	Signed `a >= b`.
kUnsignedLT	Unsigned `a < b`.
kUnsignedLE	Unsigned `a <= b`.
kUnsignedGT	Unsigned `a > b`.
kUnsignedGE	Unsigned `a >= b`.
kBTZero	Tested bit is zero.
kBTNotZero	Tested bit is not zero.
kAlways	No condition code (always).
kMaxValue	Maximum value of `CondCode`.

arm::OffsetMode : uint32_tenum class[¶]

Memory offset mode.

Describes either fixed, pre-index, or post-index offset modes.

Constant	Description
kFixed	Fixed offset mode (either no index at all or a regular index without a write-back).
kPreIndex	Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
kPostIndex	Post-index "[BASE], #Offset {, <shift>}" with write-back.

arm::ShiftOp : uint32_tenum class[¶]

Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.

Note

The constants are AsmJit specific. The first 5 values describe real constants on ARM32 and AArch64 hardware, however, the addition constants that describe extend modes are specific to AsmJit and would be translated to the AArch64 specific constants by the assembler.

Constant	Description
kLSL	Shift left logical operation (default). Available to all ARM architectures.
kLSR	Shift right logical operation. Available to all ARM architectures.
kASR	Shift right arithmetic operation. Available to all ARM architectures.
kROR	Rotate right operation (AArch32 only).
kRRX	Rotate right with carry operation (encoded as `ShiftOp::kROR` with zero) (AArch32 only).
kMSL	Shift left by filling low order bits with ones.
kUXTB	UXTN extend register operation (AArch64 only).
kUXTH	UXTH extend register operation (AArch64 only).
kUXTW	UXTW extend register operation (AArch64 only).
kUXTX	UXTX extend register operation (AArch64 only).
kSXTB	SXTB extend register operation (AArch64 only).
kSXTH	SXTH extend register operation (AArch64 only).
kSXTW	SXTW extend register operation (AArch64 only).
kSXTX	SXTX extend register operation (AArch64 only).

CondCode arm::reverse_cond(
CondCode cond
)constexprstaticnodiscardnoexcept[¶]

Reverses a condition code (reverses the corresponding operands of a comparison).

CondCode arm::negate_cond(
CondCode cond
)constexprstaticnodiscardnoexcept[¶]

Negates a condition code.

ARM Commons [¶]

Namespaces

Emitters

Supported Instructions

ARM Operands

Memory Operands

Other

Namespaces

Classes

Enumerations

Functions

arm::CondCode : uint8_tenum class[¶]

Note

arm::OffsetMode : uint32_tenum class[¶]

arm::ShiftOp : uint32_tenum class[¶]

Note

CondCode arm::reverse_cond(CondCode cond)constexprstaticnodiscardnoexcept[¶]

CondCode arm::negate_cond(CondCode cond)constexprstaticnodiscardnoexcept[¶]

CondCode arm::reverse_cond(
CondCode cond
)constexprstaticnodiscardnoexcept[¶]

CondCode arm::negate_cond(
CondCode cond
)constexprstaticnodiscardnoexcept[¶]