ARM Commons

ARM commons shared between AArch32 and AArch64.

Namespaces

• arm - arm namespace provides common functionality for both AArch32 and AArch64 backends.
• a32 - a32 namespace provides support for AArch32 architecture. In addition it includes arm namespace, so you can only use a single namespace when targeting AArch32 architecture.
• a64 - a64 namespace provides support for AArch64 architecture. In addition it includes arm namespace, so you can only use a single namespace when targeting AArch64 architecture.

Emitters

• AArch32
  • a32::Assembler - AArch32 assembler (must read, provides examples).
  • a32::Builder - AArch32 builder.
  • a32::Compiler - AArch32 compiler.
  • a32::Emitter - AArch32 emitter (abstract).
• AArch64
  • a64::Assembler - AArch64 assembler (must read, provides examples).
  • a64::Builder - AArch64 builder.
  • a64::Compiler - AArch64 compiler.
  • a64::Emitter - AArch64 emitter (abstract).

Supported Instructions

• AArch32:
  • Emitters:
    • a32::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch32 emitters.
  • Instruction representation:
    • a32::Inst::Id - instruction identifiers.
• AArch64:
  • Emitters:
    • a64::EmitterExplicitT - Provides all instructions that use explicit operands, provides also utility functions. The member functions provided are part of all AArch64 emitters.
  • Instruction representation:
    • a64::Inst::Id - instruction identifiers.

Register Operands

• arm::Reg - Base class of all AArch32/AArch64 registers.
  • a32::Gp - 32-bit general purpose register used by AArch32:
  • a64::Gp - 32-bit or 64-bit general purpose register used by AArch64:
    • a64::GpW - 32-bit register (AArch64).
    • a64::GpX - 64-bit register (AArch64).
  • arm::BaseVec - Base vector (SIMD) register.
    • a32::Vec - Vector (SIMD) register (AArch32):
      • a32::VecS - 32-bit SIMD register (AArch32).
      • a32::VecD - 64-bit SIMD register (AArch32).
      • a32::VecV - 128-bit SIMD register (AArch32).
    • a64::Vec - Vector (SIMD) register (AArch64):
      • a64::VecB - 8-bit SIMD register (AArch64).
      • a64::VecH - 16-bit SIMD register (AArch64).
      • a64::VecS - 32-bit SIMD register (AArch64).
      • a64::VecD - 64-bit SIMD register (AArch64).
      • a64::VecV - 128-bit SIMD register (AArch64).

Memory Operands

• arm::Mem - AArch32/AArch64 memory operand that provides support for all ARM addressing features including base, index, pre/post increment, and ARM-specific shift addressing and index extending.

Other

• arm::Shift - Shift operation and value (both AArch32 and AArch64).
• arm::DataType - Data type that is part of an instruction in AArch32 mode.
• arm::Utils - Utilities that can help during code generation for AArch32 and AArch64.

Namespaces

namespace arm

namespace arm::Utils

Classes

struct arm::RegTraits<kRegType>

class arm::Reg

class arm::BaseVec

class arm::Mem

struct arm::Utils::LogicalImm

class arm::Shift

Enumerations

enum class arm::CondCode : uint8_t

enum class arm::OffsetMode : uint32_t

enum class arm::ShiftOp : uint32_t

Functions

static constexpr CondCode arm::negateCond(CondCode cond) noexcept

Shift Operation Construction

static constexpr Shift arm::lsl(uint32_t value) noexcept

static constexpr Shift arm::lsr(uint32_t value) noexcept

static constexpr Shift arm::asr(uint32_t value) noexcept

static constexpr Shift arm::ror(uint32_t value) noexcept

static constexpr Shift arm::rrx() noexcept

static constexpr Shift arm::msl(uint32_t value) noexcept

Memory Operand Construction

static constexpr Mem arm::ptr(uint64_t base) noexcept

Enumeration Type Documentation

class arm::CondCode : uint8_tenumstrong

Condition code (both AArch32 & AArch64).

Note

This enumeration doesn't match condition code that is used in AArch32/AArch64 opcodes. In general this condition code is encoded as (cc - 2) & 0xF so that kAL condition code is zero and encoded as 0xE in opcode. This makes it easier to use a condition code as an instruction modifier that defaults to 'al'.

Constant	Description
kAL	(no condition code) (always)
kNA	(not available) (special)
kEQ	Z==1 (any_sign ==)
kNE	Z==0 (any_sign !=)
kCS	C==1 (unsigned >=)
kHS	C==1 (unsigned >=)
kLO	C==0 (unsigned < )
kCC	C==0 (unsigned < )
kMI	N==1 (is negative)
kPL	N==0 (is positive or zero)
kVS	V==1 (is overflow)
kVC	V==0 (no overflow)
kHI	C==1 & Z==0 (unsigned > )
kLS	C==0 | Z==1 (unsigned <=)
kGE	N==V (signed >=)
kLT	N!=V (signed < )
kGT	Z==0 & N==V (signed > )
kLE	Z==1 | N!=V (signed <=)
kSign	Sign.
kNotSign	Not sign.
kOverflow	Signed overflow.
kNotOverflow	Not signed overflow.
kEqual	Equal a == b.
kNotEqual	Not Equal a != b.
kZero	Zero (alias to equal).
kNotZero	Not Zero (alias to Not Equal).
kNegative	Negative.
kPositive	Positive or zero.
kSignedLT	Signed a < b.
kSignedLE	Signed a <= b.
kSignedGT	Signed a > b.
kSignedGE	Signed a >= b.
kUnsignedLT	Unsigned a < b.
kUnsignedLE	Unsigned a <= b.
kUnsignedGT	Unsigned a > b.
kUnsignedGE	Unsigned a >= b.
kAlways	No condition code (always).
kMaxValue	Maximum value of CondCode.

class arm::OffsetMode : uint32_tenumstrong

Memory offset mode.

Describes either fixed, pre-index, or post-index offset modes.

Constant	Description
kFixed	Fixed offset mode (either no index at all or a regular index without a write-back).
kPreIndex	Pre-index "[BASE, #Offset {, <shift>}]!" with write-back.
kPostIndex	Post-index "[BASE], #Offset {, <shift>}" with write-back.

class arm::ShiftOp : uint32_tenumstrong

Shift operation predicate (ARM) describes either SHIFT or EXTEND operation.

Note

The constants are AsmJit specific. The first 5 values describe real constants on ARM32 and AArch64 hardware, however, the addition constants that describe extend modes are specific to AsmJit and would be translated to the AArch64 specific constants by the assembler.

Constant	Description
kLSL	Shift left logical operation (default). Available to all ARM architectures.
kLSR	Shift right logical operation. Available to all ARM architectures.
kASR	Shift right arithmetic operation. Available to all ARM architectures.
kROR	Rotate right operation (AArch32 only).
kRRX	Rotate right with carry operation (encoded as ShiftOp::kROR with zero) (AArch32 only).
kMSL	Shift left by filling low order bits with ones.
kUXTB	UXTN extend register operation (AArch64 only).
kUXTH	UXTH extend register operation (AArch64 only).
kUXTW	UXTW extend register operation (AArch64 only).
kUXTX	UXTX extend register operation (AArch64 only).
kSXTB	SXTB extend register operation (AArch64 only).
kSXTH	SXTH extend register operation (AArch64 only).
kSXTW	SXTW extend register operation (AArch64 only).
kSXTX	SXTX extend register operation (AArch64 only).

Function Documentation

Shift arm::lsl(uint32_t value)constexprstaticconstexprnoexcept

Constructs a LSL #value shift (logical shift left).

Shift arm::lsr(uint32_t value)constexprstaticconstexprnoexcept

Constructs a LSR #value shift (logical shift right).

Shift arm::asr(uint32_t value)constexprstaticconstexprnoexcept

Constructs a ASR #value shift (arithmetic shift right).

Shift arm::ror(uint32_t value)constexprstaticconstexprnoexcept

Constructs a ROR #value shift (rotate right).

Shift arm::rrx()constexprstaticconstexprnoexcept

Constructs a RRX shift (rotate with carry by 1).

Shift arm::msl(uint32_t value)constexprstaticconstexprnoexcept

Constructs a MSL #value shift (logical shift left filling ones).

Mem arm::ptr(uint64_t base)constexprstaticconstexprnoexcept

Creates [base] absolute memory operand (AArch32 or AArch64).

Note

The concept of absolute memory operands doesn't exist on ARM, the ISA only provides PC relative addressing. Absolute memory operands can only be used if it's known that the PC relative offset is encodable and that it would be within the limits. Absolute address is also often output from disassemblers, so AsmJit supports it to make it possible to assemble such output back.

CondCode arm::negateCond(CondCode cond)constexprstaticconstexprnoexcept

Negates a condition code.