AsmJit
Low-Latency Machine Code Generation
Public utilities and helpers for targeting AArch32 and AArch64 architectures.
Encodes a 12-bit immediate part of opcode that ise used by a standard 32-bit ARM encoding.
Encodes the given imm
value of the given width
to a logical immediate value represented as N, S, and R fields and writes these fields to out
.
Encoding Table:
Returns true if the given imm
value is encodable as a logical immediate.
The width
argument describes the width of the operation, and must be either 32 or 64. This function can be used to test whether an immediate value can be used with AND, ANDS, BIC, BICS, EON, EOR, ORN, and ORR instruction.
Returns true if the given imm
value is encodable as an immediate with add
and sub
instructions on AArch64.
These two instructions can encode 12-bit immediate value optionally shifted left by 12 bits.
Returns true if the given imm
value is a byte mask.
Byte mask has each byte part of the value set to either 0x00 or 0xFF. Some ARM instructions accept immediates that form a byte-mask and this function can be used to verify that the immediate is encodable before using the value.
Returns true if the given half precision floating point val
can be encoded as ARM IMM8 value, which represents a limited set of floating point immediate values, which can be used with FMOV instruction.
The floating point must have bits distributed in the following way:
Returns true if the given single precision floating point val
can be encoded as ARM IMM8 value, which represents a limited set of floating point immediate values, which can be used with FMOV instruction.
The floating point must have bits distributed in the following way:
This is an overloaded member function, provided for convenience. It differs from the above function only in what argument(s) it accepts.
Returns true if the given double precision floating point val
can be encoded as ARM IMM8 value, which represents a limited set of floating point immediate values, which can be used with FMOV instruction.
The floating point must have bits distributed in the following way:
This is an overloaded member function, provided for convenience. It differs from the above function only in what argument(s) it accepts.
Encodes a double precision floating point value into IMM8 format.
isFP64Imm8(val) == true
so it doesn't perform any checks of the value and just rearranges some bits into Imm8 order. This is an overloaded member function, provided for convenience. It differs from the above function only in what argument(s) it accepts.