IndexUJIT

UJIT [¶]

Universal JIT - abstracts X86|X86_64 and AArch64 code generation.

Namespaces

Typedefs

Enumerations

Functions

Variables

ujit::ScalarOpBehavior : uint8_tenum classstrong[¶]

The behavior of a floating point scalar operation.

ConstantDescription
kZeroing 

The rest of the elements are zeroed, only the first element would contain the result (AArch64).

kPreservingVec128 

The rest of the elements are unchanged, elements above 128-bits are zeroed.

ujit::FMinFMaxOpBehavior : uint8_tenum classstrong[¶]

The behavior of a floating point min/max instructions when comparing against NaN.

ConstantDescription
kFiniteValue 

Min and max selects a finite value if one of the compared values is NaN.

kTernaryLogic 

Min and max is implemented like if a <|> b ? a : b.

ujit::FMAddOpBehavior : uint8_tenum classstrong[¶]

The behavior of floating point madd instructions.

ConstantDescription
kNoFMA 

FMA is not available, thus madd is translated into two instructions (MUL + ADD).

kFMAStoreToAny 

FMA is available, the ISA allows to store the result to any of the inputs (X86|X86_64).

kFMAStoreToAccumulator 

FMA is available, the ISA always uses accumulator register as a destination register (AArch64).

ujit::DataWidth : uint8_tenum classstrong[¶]

SIMD data width.

ujit::VecWidth : uint8_tenum classstrong[¶]

Vector register width.

ConstantDescription
k128 

128-bit vector register (baseline, SSE/AVX, NEON, ASIMD, etc...).

k256 

256-bit vector register (AVX2+).

k512 

512-bit vector register (AVX512_DQ & AVX512_BW & AVX512_VL).

k1024 

1024-bit vector register (no backend at the moment).

ujit::Bcst : uint8_tenum classstrong[¶]

Broadcast width.

ujit::UniOpRR : uint32_tenum classstrong[¶]

Arithmetic operation having 2 operands (dst, src).

ujit::UniOpRRR : uint32_tenum classstrong[¶]

Arithmetic operation having 3 operands (dst, src1, src2).

ujit::UniOptFlags : uint32_tenum classstrong[¶]

Pipeline optimization flags used by UniCompiler.

ConstantDescription
kNone 

No flags.

kMaskOps8Bit 

CPU has instructions that can perform 8-bit masked loads and stores.

kMaskOps16Bit 

CPU has instructions that can perform 16-bit masked loads and stores.

kMaskOps32Bit 

CPU has instructions that can perform 32-bit masked loads and stores.

kMaskOps64Bit 

CPU has instructions that can perform 64-bit masked loads and stores.

kFastVpmulld 

CPU provides low-latency 32-bit multiplication (AMD CPUs).

kFastVpmullq 

CPU provides low-latency 64-bit multiplication (AMD CPUs).

kFastGather 

CPU performs hardware gathers faster than a sequence of loads and packing.

kFastStoreWithMask 

CPU has fast stores with mask.

Note

This is a hint to the compiler to emit a masked store instead of a sequence having branches.

template<typename T>
struct ujit::ASMJIT_ALIGNAS(
8
)[1/4][¶]

A 64-bit vector constant of type T aligned to 64 bits.

template<typename T>
struct ujit::ASMJIT_ALIGNAS(
16
)[2/4][¶]

A 128-bit vector constant of type T aligned to 128 bits.

template<typename T>
struct ujit::ASMJIT_ALIGNAS(
32
)[3/4][¶]

A 256-bit vector constant of type T aligned to 256 bits.

template<typename T>
struct ujit::ASMJIT_ALIGNAS(
64
)[4/4][¶]

A 512-bit vector constant of type T aligned to 512 bits.