asmjit::arm::Gp Class Reference
Inheritance diagram for asmjit::arm::Gp:
asmjit::arm::Reg asmjit::BaseReg asmjit::Operand asmjit::Operand_ asmjit::arm::GpW asmjit::arm::GpX

General purpose register (ARM).

Public Types

- Public Types inherited from asmjit::BaseReg
- Public Types inherited from asmjit::Operand_

Member Functions

- Public Member Functions inherited from asmjit::arm::Reg
- Public Member Functions inherited from asmjit::BaseReg
- Public Member Functions inherited from asmjit::Operand
- Public Member Functions inherited from asmjit::Operand_

Additional Inherited Members

- Public Attributes inherited from asmjit::Operand_
- Static Public Member Functions inherited from asmjit::arm::Reg
- Static Public Member Functions inherited from asmjit::BaseReg
- Static Public Member Functions inherited from asmjit::Operand_

Member Enumeration Documentation

arm::Gp::Id : uint32_tenum

Special register id.

ConstantDescription
kIdOs 

Register that depends on OS, could be used as TLS offset.

kIdFp 

Frame pointer.

kIdLr 

Link register.

kIdSp 

Stack register id.

kIdZr 

Zero register id.

Although zero register has the same id as stack register it has a special treatment, because we need to be
able to distinguish between these two at API level. Some intructions were designed to be used with SP and
some other with ZR - so we need a way to distinguish these two to make sure we emit the right thing.

The number 63 is not random, when you perform `id & 31` you would always get 31 for both SP and ZR inputs,
which is the identifier used by AArch64 ISA to encode either SP or ZR depending on the instruction.