AsmJit
Low-Latency Machine Code Generation
Read/Write information of an instruction.
Resets this RW information to all zeros.
Returns flags associated with the instruction, see InstRWFlags.
Tests whether the instruction flags contain flag
.
Tests whether the instruction flags contain InstRWFlags::kMovOp.
Returns a mask of CPU flags read.
Returns a mask of CPU flags written.
Returns the CPU feature required to replace a register operand with memory operand.
If the returned feature is zero (none) then this instruction either doesn't provide memory operand combination or there is no extra CPU feature required.
Some AVX+ instructions may require extra features for replacing registers with memory operands, for example VPSLLDQ instruction only supports vpslldq reg, reg, imm
combination on AVX/AVX2 capable CPUs and requires AVX-512 for vpslldq reg, mem, imm
combination.
Returns RW information of extra register operand (extraReg).
Returns RW information of all instruction's operands.
Returns RW information of the operand at the given index
.
Returns the number of operands this instruction has.
Instruction flags (there are no flags at the moment, this field is reserved).
CPU flags read.
CPU flags written.
Count of operands.
CPU feature required for replacing register operand with memory operand.
Reserved for future use.
Read/Write info of extra register (rep{} or kz{}).
Read/Write info of instruction operands.